
`include "defines.v"

//----------------------------------------------------------------
//Module Name : intr_pro.v
//Description of module:
//
//----------------------------------------------------------------
//Designer:	Tang Pengyu
//Date: 2021/10/03/09:23 
//----------------------------------------------------------------

module	intr_pro(
	input	clk,
	input	if_fetched,
	input	MTIP,
	output	reg time_intr_r
);
reg		if_fetched_r1;
reg		if_fetched_r2;
reg		if_fetched_r3;
always @(posedge clk)	begin
	if_fetched_r1 <= if_fetched;
	if_fetched_r2 <= if_fetched_r1;
	if_fetched_r3 <= if_fetched_r2;
end
always @(posedge if_fetched_r3)	begin
	time_intr_r <= MTIP ? 1'b1 : 1'b0;
end

endmodule